A common problem affecting the performance of integrated circuits and systems using integrated circuits is the inductance on the power input pins. At the system level, input pin inductance problems are alleviated by adding bypass capacitors between the power and ground traces on the printed circuit board adjacent the power and ground pins of the integrated circuit packages. While this eliminates the PC board inductance, the integrated circuit package inductance due to the package power input pin inductance and the inductance of the bond wire coupling the power input pin to the integrated circuit remains. These package inductances may range from 3 nH to over 20 nH, depending on the package type, the number and type of pins used for power input and the number and spacing of the associated bond wires.
When the outputs of an integrated circuit switch, internal spikes of one ampere or higher may be encountered, lasting from one to two nanoseconds. These spikes result in a change of input current between 0.5 to 1.5 amp/ns. The change in input current can result in a significant voltage drop across the inductance of the power input pin and associated bond wire as a function of their inductance, since the voltage across an inductor behaves according to the formula V.sub.L =L di(t)/dt where V.sub.L is the voltage across the inductor, L is the inductance and di/dt is the change in current with time through the inductor. As an example, a twenty-eight pin package having an input power pin with an inductance of 8 nH switching at a rate of 0.5 amp/ns will develop a four volt drop across the power input pin. Such a drop is not practical for an integrated circuit operating on a 5 volt nominal power supply.
One method of reducing the voltage drop across the power input inductance is to reduce the rate at which the output switches the associated output loads. In the example given above, if the output switching rate is reduced, such that the input power switches at a reduced rate of 0.125 amps/ns, the voltage drop across the power input inductance can be reduced to 1 volt. This method has serious disadvantages in that the performance of the integrated circuit has been degraded since the output switching rate has been reduced, which may be unacceptable in many applications. Further, a voltage drop is still present which reduces the voltage available for the functional circuitry.
A second method used to help solve the problems of inductance on the input power pins is to add a power to ground bypass capacitor in the integrated circuit package during the mounting and bonding procedure. These discrete capacitors are commonly known as "chip" capacitors which effectively couple the power and ground pins so that the switching current is passed through both the inductors created by the power input pin and the ground pin, thereby cancelling the loss through the power input pin. A number of disadvantages are inherent with this method, however. The assembly cost is increased due to the additional steps of mounting and bonding the added capacitor. The reliability of the overall integrated circuit package may be significantly reduced since the added capacitor is usually less reliable then the associated integrated circuit. Further, the lower cost capacitors, which would be desirable for use in a highly competitive market, do not have the frequency response needed and may even add an additional 2 nH or more of series inductance themselves. When this series inductance of the bypass capacitor is added with the inductance of the bonding wires required to connect the capacitor with the associated pins, the solution becomes marginal. Finally, the internal resistances from the pins, bonding wires and the capacitor itself may be high enough to adversely affect the performance of the added capacitor.
Thus, the need has arisen for apparatus and methods for reducing the inductance of the input power pins such that maximum internal voltage can be achieved while maintaining fast output current switching speed and high reliability.